Z2.02-2779 (SBIR 2022-1)
Design and Formal Verification of a Fault-Tolerant RISC-V Processor Core Augmented to Accelerate Image and Science Data Processing
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$0.00 |
IL |
STMD |
JPL |
2022 |
T11.01-9878 (STTR 2015-1)
Advanced Tools for Effective Automated Test Generation
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$0.00 |
IL |
STTR |
ARC |
2015 |
A1.06-9149 (SBIR 2012-1)
Formal Verification of Interactions of the RTOS, Memory System, and Application Programs at the PowerPC 750 Binary Code Level
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$125,000.00 |
IL |
ARMD |
LaRC |
2012 |
A1.06-8686 (SBIR 2012-1)
Scalable Parallel Algorithms for Formal Verification of Software
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$125,000.00 |
IL |
ARMD |
LaRC |
2012 |
A1.20-8922 (SBIR 2011-1)
Scalable Parallel Algorithms for Formal Verification of Software
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$125,000.00 |
IL |
ARMD |
ARC |
2011 |
O1.03-8382 (SBIR 2009-1)
Reconfigurable VLIW Processor for Software Defined Radio
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$100,000.00 |
IL |
SOMD |
AFRC |
2009 |
O1.03-8382 (SBIR 2009-2)
Reconfigurable VLIW Processor for Software Defined Radio
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$600,000.00 |
IL |
SOMD |
GRC |
2009 |
X1.02-8609 (SBIR 2008-1)
An Efficient Parallel SAT Solver Exploiting Multi-Core Environments
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$100,000.00 |
IL |
ESMD |
ARC |
2008 |
X1.02-8609 (SBIR 2008-2)
An Efficient Parallel SAT Solver Exploiting Multi-Core Environments
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$600,000.00 |
IL |
ESMD |
ARC |
2008 |
X1.02-8523 (SBIR 2007-1)
Efficient Techniques for Formal Verification of PowerPC 750 Executables
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$100,000.00 |
IL |
ESMD |
ARC |
2007 |
X1.02-8523 (SBIR 2007-2)
Efficient Techniques for Formal Verification of PowerPC 750 Executables
|
Aries Design Automation, LLC
Miroslav Velev,
miroslav.velev@aries-da.com
|
$600,000.00 |
IL |
ESMD |
ARC |
2007 |