A VLSI Digital Tester Based Upon A Single Custom Chip Per Individual
Project Title:A VLSI Digital Tester Based Upon A Single Custom Chip Per Individual
Company:Bonneville Scientific, Inc.
Salt Lake City, UT 84105
Principal Investigator:Grahn, Allen R.
In this Phase I, six-month feasibility study we propose to generate a plan for a
system architecture for a digital VLSI chip tester. The tester will e designed to
interface to the design workstation to allow interactive debugging of prototype circuits
and subsequent down loading of test patterns and expected results to a production
VLSI tester. The tester will be low in cost because it will not perform analog testing
and because each individual pin of the device under test will be directly tested
by a dedicated testing integrated circuit. The functional design of this testing
chip will be generated, the circuit will be ocmpletely designed using Path Programmable
Logic, and it will be simulated during Phase I. The chip will be fabricated and
the complete tester system (hardware and software) will be completed in Phase II.