NASA SBIR 2021-I Solicitation

Proposal Summary

Proposal Number:          21-1- H9.05-2243
Subtopic Title:
      Transformational Communications Technology
Proposal Title:
      A Charge Ramping Quantizer

Small Business Concern

Pacific Microchip Corporation
3916 Sepulveda Boulevard, #108, Culver City, CA 90230
(310) 683-2628                                                                                                                                                                                

Principal Investigator:

Dr. Reza Ramezani
3916 Sepulveda Boulevard, #108, CA 90230 - 4650
(310) 683-2628                                                                                                                                                                                

Business Official:

Ieva Ivanauskas
3916 Sepulveda Boulevard, #108, CA 90230 - 4650
(310) 683-2628                                                                                                                                                                                

Summary Details:

Estimated Technology Readiness Level (TRL) :                                                                                                                                                          
Begin: 2
End: 3
Technical Abstract (Limit 2000 characters, approximately 200 words):

Pacific Microchip Corp. proposes to develop an ADC implementing fundamentally new architecture employing a single stage voltage-to-charge-to-digital converter based on a charge ramping quantizer (CRQ). The CRQ removes traditional barriers such as large number of comparators (Flash architecture), slow binary search (SAR architecture), power hungry and slow continuous-time comparators and large silicon area consuming time-to-digital converters (temporal ADC). By removing these barriers and taking full benefit of modern CMOS processes, the CRQ offers a high sampling rate at greatly reduced power consumption. A single sub-ADC based on this architecture demonstrates over 4 times speed improvement compared to a SAR ADC. The project will target 8-bit resolution and 56GS/s rate. Instead of overdesigning, when seeking to maximize the performance, the ADC will rely on parameter calibration using a built-in CPU. On-chip phase locked loops (PLLs) will be used for clock synthesis. For convenient interfacing with field programmable gate arrays (FPGAs) at up to 64x8.8Gb/s, the ADC will include a JESD204B standard compliant interface. Phase I work will provide the proof of ADC feasibility – critical blocks will be implemented and verified at the targeted technology node. At Phase II, a silicon proven prototype ADC will be provided.

Potential NASA Applications (Limit 1500 characters, approximately 150 words):


  • Space-based wireless satellite-to-satellite communication systems
  • Space-to-Earth communication systems
  • Earth observation instrumentation
Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words):
  • Future communication systems
  • Multiple input multiple output (MIMO) systems
  • Synthetic aperture radars (SARs) in active sensors
  • Passive microwave sensors
  • Receivers for SDRs and 5G communication systems
  • Fiber optic communication systems for 100-400Gb/s
  • Surveillance instruments
  • Communication and navigation satellites
  • Test instruments such as digital sampling scopes
Duration:     6

Form Generated on 04/06/2021 12:15:12