NASA SBIR 2020-I Solicitation

Proposal Summary


PROPOSAL NUMBER:
 20-1- Z2.02-5725
SUBTOPIC TITLE:
 High Performance Space Computing Technology
PROPOSAL TITLE:
 Fault Tolerant Parallel Processing for HPSC
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Antara Teknik, LLC
5233 Castlereigh Court
Granite Bay, CA 96746
(916) 622-6960

Principal Investigator (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Mehmet Adalier
E-mail:
madalier@antarateknik.com
Address:
5233 Castlereigh Court Granite Bay, CA 96746 - 7123
Phone:
(916) 622-6960

Business Official (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Mehmet Adalier
E-mail:
madalier@antarateknik.com
Address:
5233 Castlereigh Court Granite Bay, CA 96746 - 7123
Phone:
(916) 622-6960
Estimated Technology Readiness Level (TRL) :
Begin: 3
End: 4
Technical Abstract (Limit 2000 characters, approximately 200 words)

NASA's intention is that the new SOA for in space processing will be High Performance Spaceflight Computing (HPSC) Chiplet based. The HPSC formulation study identified several use cases including autonomy, human spaceflight, robotics, and science mission scenarios, which require significantly higher performance computing. In order to maximize performance to power ratio further efforts are required to R&D a fault tolerant middleware for HPSC Chiplet Parallel Processing. This middleware needs to include Arm Cortex A53 general purpose register and Neon Single instruction Multiple Data (SIMD) optimized math and I/O kernels and library routines. During the Phase I effort, Antara will investigate and document a repeatable and deterministic methodology to identify and profile math and I/O kernel performance bottlenecks that significantly affect the performance of HPSC representative applications. Antara will establish criteria to prioritize the list of kernels for optimization and optimize several relevant kernels to show the feasibility of the methodology and scale potential. Additionally, Antara will perform systematic performance analysis and initial optimization of the math and I/O kernels and libraries that relate to HPC representative application SAR processing and report pre- and post-optimization performance indicators. Antara will bench-test its technology on relevant A53 based boards to establish and demonstrate deterministic performance to achieve TRL 4. The proposed innovation is significant and will enable the rapid development and infusion of a flight qualifiable Fault Tolerant Parallel Processing Package for the HPSC Chiplet. Successful infusion of the cross-cutting innovation will enhance the HPSC Ecosystem and support major programs. The innovation will support potential near-term infusion targets such as Mars Fetch Rover, Lunar Gateway, SPLICE/Lunar Lander and the Moon to Mars campaign.

Potential NASA Applications (Limit 1500 characters, approximately 150 words)

Antara's robust, fault-tolerant, and optimized Math and I/O Kernel Middleware Library will be a cross-cutting capability that will provide a flight qualifiable Fault Tolerant Parallel Processing Package for the HPSC Chiplet. The innovation will enhance the HPSC Ecosystem and directly support potential near-term infusion targets such as the Mars Fetch Rover,  Lunar Gateway, and other long-term NASA applications and missions, including the Moon to Mars Campaign. 

Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words)

Commercial space companies, agencies, defense and primes adopting the HPSC Chiplet will be able to license Antara's innovation for efficient and high performance parallel and heterogeneous processing. Applicable use-cases will include efficient Synthetic Aperture Radar processing, Imaging Spectrometers, Close Proximity Operations/Formation Flying and Augmented Reality for Recognition.

Duration: 6

Form Generated on 06/29/2020 21:05:47