NASA SBIR 2020-I Solicitation

Proposal Summary


PROPOSAL NUMBER:
 20-1- Z2.02-4527
SUBTOPIC TITLE:
 High Performance Space Computing Technology
PROPOSAL TITLE:
 NN_Co-Processor
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Silicon Space Technology Corporation
1501 South MoPac Expressway, Suite 350
Austin, TX 78746
(512) 347-1800

Principal Investigator (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Jim Carlquist
E-mail:
jcarlquist@voragotech.com
Address:
1501 South MoPac Expressway, Suite 350 Austin, TX 78746 - 6966
Phone:
(512) 576-8210

Business Official (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Garry Nash
E-mail:
gnash@siliconspacetech.com
Address:
1501 South MoPac Expressway, Suite 350 Austin, TX 78746 - 6966
Phone:
(631) 559-1550
Estimated Technology Readiness Level (TRL) :
Begin: 1
End: 4
Technical Abstract (Limit 2000 characters, approximately 200 words)

This fault tolerant SoC architecture focuses on signal and data processing while offering a systematic way to improve mission communication and data processing capabilities, enhance computing performance and reduce memory requirements. This technology will allow for increased speed, energy efficiency and higher performance for computing in unknown and un-characterized space environments including the Moon and Mars and beyond.

 

We will mitigate against different types of radiation effects using proven circuit hardware and process-based techniques. These techniques include Triple-Mode Redundancy (TMR), Dual-Interlocked Cell (DICE) register elements and clock glitch filter circuit implementations as well as VORAGO’s HARDSIL® process that prevents radiation-induced latch-up. For memories, we plan to implement Error Detection and Correction (EDAC) and scrubbing. We will evaluate and document the level of protection required by each rad-hard zone on the device, how to mitigate against radiation effects in each zone and calculate the expected radiation performance of each zone and the complete IC.

 

There are some obvious features of the SoC that we are quite certain will be included in the final device definition. These include the ARM Cortex M core, the ARM Ethos core, EDAC-protected SRAM (that is required to execute the software) and UART, I2C and SPI serial communications blocks. We may also include an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) as well as a SpaceWire interface and a MIL-STD-1553B bus interface. Until the use-case analysis is complete, we will investigate what other industry-standard IP blocks to include on the final IC. These will likely include further communications modules to interface with common spacecraft bus systems and control-oriented IP blocks such as timers with Pulse Width Modulation (PWM) outputs. It is possible to include other IP blocks and peripherals to provide a full mixed-signal SoC.

Potential NASA Applications (Limit 1500 characters, approximately 150 words)

NASA applications will include miniaturized instruments and subsystems that must operate in harsh environments, interplanetary CubeSats and SmallSats, outer planet instruments, and heliophysics missions to harsh radiation environments. Neural-network and machine learning capabilities are required for robotic vision and system health management in future autonomous robotic systems.

 

Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words)

The greatest potential for the next computing revolution lies in scaling AI to the billions of smaller, power-constrained endpoint devices, while making the product RADHARD. Innovative signal processing and ML techniques will open up new opportunities for SoC architects to deliver these new levels of efficient AI performance for microcontrollers that are in the space market.

Duration: 6

Form Generated on 06/29/2020 21:12:42