NASA SBIR 2020-I Solicitation

Proposal Summary

 20-1- S3.08-4526
 Command, Data Handling, and Electronics
 Fault-Tolerant RISC-V SoC
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Silicon Space Technology Corporation
1501 South MoPac Expressway, Suite 350
Austin, TX 78746
(512) 347-1800

Principal Investigator (Name, E-mail, Mail Address, City/State/Zip, Phone)

Jim Carlquist
1501 South MoPac Expressway, Suite 350 Austin, TX 78746 - 6966
(512) 576-8210

Business Official (Name, E-mail, Mail Address, City/State/Zip, Phone)

Garry Nash
1501 South MoPac Expressway, Suite 350 Austin, TX 78746 - 6966
(631) 559-1550
Estimated Technology Readiness Level (TRL) :
Begin: 1
End: 3
Technical Abstract (Limit 2000 characters, approximately 200 words)

We will develop a fault-tolerant architecture and IC specification for a RISC-V open instruction set architecture (ISA) based System-on-Chip (SoC). We will implement the IC as a monolithic SoC to optimize the size, weight and power consumption over that which can be accomplished using an FPGA. The IC architecture will be based upon industry standard, state-of-the-art IP and will be scalable to easily allow the creation of further ICs with different IP blocks, scalable fault-tolerance and reuse of software across different products based upon the base architecture.

VORAGO Technologies has experience of implementing the RISC-V ISA on a Microsemi RTG4 FPGA. The existing VORAGO product portfolio consists of rad-hard Arm Cortex-M MCUs. We can satisfy a demand for fault-tolerant, small-footprint, low-power RISC-V based SoCs by consolidating the RISC-V ISA with the radiation-hardened SoC technology (HARDSIL®) that has already been proven by VORAGO. 

Besides replacing the Arm Cortex-M core with the RISC-V ISA, we will further optimize the fault-tolerant topology of the SoC to achieve a high level of radiation performance that is scalable for use in the harshest environments. This will allow all IP to be implemented in Triple Modular Redundant (TMR) form if required. We plan to use the industry-standard AMBA bus on the SoC to allow easy integration of industry-standard IP blocks. The IP will be implemented in Register Transfer Level (RTL) code. We will implement this SoC device in the smallest possible package and it will provide the following advantages over RISC-V implementations in FPGAs:

  • Smaller package footprint
  • Lower power consumption
  • Lighter weight
  • Better or equivalent radiation performance
  • High performance due to tightly-coupled SoC integration of IP blocks. 
  • Smaller die size and low unit cost of SoC over FPGAs
  • Scalable architecture to facilitate the creation of a family of products with different functional capabilities that can re-use the same RISC-V software base
Potential NASA Applications (Limit 1500 characters, approximately 150 words)

A successful outcome to this project will result in a radiation-hardened RISC-V SoC IC that can be qualified for space flight and provide NASA with a state-of-the-art fault-tolerant solution for missions across all Science Mission Directorate divisions. Applications will include miniaturized instruments and subsystems that must operate in harsh environments, interplanetary CubeSats and SmallSats, outer planet instruments and heliophysics missions to harsh radiation environments.

Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words)

We expect that the device that we are proposing will be extremely interesting to US Government and commercial aerospace customers who have already expressed an interest in using the RISC-V ISA. We expect that this IC will be used in similar applications as NASA use at customers such as Air Force, Lockheed Martin, Raytheon, Northrop Grumman, SSL, SEAKR, Bigelow Aerospace, Blue Origin and Spire.

Duration: 6

Form Generated on 06/29/2020 21:08:33