Adsantec will develop a single package Application Specific Integrated Circuit, capable surviving and maintaining performance in high radiation environments (> 1 Mrad), including enhanced low dose rate sensitivity. The DAC will have a sampling rate greater than 1 Gb/s with effective number of bits >6. The design will be based on the company’s proprietary reconfigurable DAC architecture, which incorporates a patented pseudo straight forward synchronization algorithm (PSFS) and a patented rad hard clock recovery/Phase Lock Loop Scheme.
The proposed PSFS will be implemented inside developed ASIC minimizing overhead during data transmission. In this design, ADSANTEC will employ proven SiGe bipolar transistor-based circuit blocks based on our hard-by-design methodology. The use of ADSANTEC’s space qualified ASIC packaging will enable fabrication and test of a TRL 7 or higher ASIC prototype at the end of Phase II.
The digitizer will greatly support the performance of NASA’s SLPS and Martian programs and can be also used for wireless communications.
The developed ASIC can be used in variety of US Air force space missions, wireless communications and measurement instrumentations.