NASA SBIR 2019-II Solicitation

Proposal Summary


PROPOSAL NUMBER:
 19-2- H6.22-3899
PHASE 1 CONTRACT NUMBER:
 80NSSC19C0467
SUBTOPIC TITLE:
 Deep Neural Net and Neuromorphic Processors for In-Space Autonomy and Cognition
PROPOSAL TITLE:
 Energy Efficient High-Throughput Neuromorphic Processor for Deep Learning
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Prixarc, LLC
2673 Commons Boulevard, Suite 55
Beavercreek, OH 45431
(937) 782-8206

PRINCIPAL INVESTIGATOR (Name, E-mail, Mail Address, City/State/Zip, Phone)
Dr. Sanjeevi Sirisha Karri
sanjeevi@prixarc.com
2673 Commons Blvd., Suite 55
Beavercreek, OH 45431 - 3833
(802) 829-8375

BUSINESS OFFICIAL (Name, E-mail, Mail Address, City/State/Zip, Phone)
Dr. Vamsy Chodavarapu
vamsy@prixarc.com
2673 Commons Blvd., Suite 55
Beavercreek, OH 45431 - 3833
(937) 782-8206

Estimated Technology Readiness Level (TRL) :
Begin: 4
End: 6
Technical Abstract (Limit 2000 characters, approximately 200 words)

The technical objective of this work is to develop a low power, high throughput neuromorphic system for online learning. The system will be based on an FPGA to enable low cost development and easy deployment. We propose to implement a transfer learning system as this will allow the FPGA to train a convolutional neural network with new data quickly and without significant hardware resource requirements. The system will be integrated with a software defined radio to be able to collect communications data continuously to be utilized for transfer learning. We have developed a prototype of the FPGA based transfer learning system in Phase I and aim to make the system more efficient, scaled up, more accurate, and general purpose so that it would be more adept at learning cognitive communications modulations in a cubesat environment. In addition to the FPGA based online learning system, we will investigate the design of accurate and efficient deep learning algorithms for the FPGA system to process cubesat communications data. This dual pronged approach of developing hardware and software will lead to the most efficient overall system, having low power, high accuracy, and high speed. We will integrate the system with a software defined radio to mimic satellite communications and carry out field tests of the system to ensure proper reliability and functionality. Our key deliverables will be the FPGA system design, deep learning algorithm evaluation and best algorithm for cognitive communications learning on the FPGA, and software defined radio integration of the FPGA system.

Potential NASA Applications (Limit 1500 characters, approximately 150 words)

This SBIR project proposes a specialized high-throughput and low power processor for deep learning algorithms geared towards cognitive radio communications systems. It is suitable for Size, Weight, and Power (SWaP) constrained environments, such as satellites and cubesats. Specific advantages include signal processing to reduce the amount of data transmitted, cognitive radio applications, and system self-diagnosis.

Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words)

The commercial product foreseen from this project is an effective, low SWaP capable deep learning processor chip.  This will have applications in multiple areas including cognitive communications, including satellites, 5G networks, smart infrastructure, autonomous systems, electronic warfare, robotics, big data analytics, bioinformatics, data mining and military systems.

Duration: 24

Form Generated on 05/04/2020 06:33:19