NASA SBIR 2019-I Solicitation

Proposal Summary

PROPOSAL NUMBER:
 19-1- S4.04-2992
SUBTOPIC TITLE:
 Extreme Environments Technology
PROPOSAL TITLE:
 Extreme Environment System Integration Techniques for Venus In-Situ Processing
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Ozark Integrated Circuits, Inc.
700 West Research Center Boulevard
Fayetteville, AR 72701- 7175
(479) 935-1600

Principal Investigator (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Mr. Nicholas Chiolino
E-mail:
nchiolino@ozarkic.com
Address:
700 W. Research Center Blvd., 1409 Fayetteville, AR 72701
Phone:
(479) 935-1600

Business Official (Name, E-mail, Mail Address, City/State/Zip, Phone)

Name:
Matt Francis
E-mail:
francis@ozarkic.com
Address:
700 West Research Center Boulevard Fayetteville, AR 72701 - 7175
Phone:
(479) 409-5201
Estimated Technology Readiness Level (TRL) :
Begin: 3
End: 5
Technical Abstract (Limit 2000 characters, approximately 200 words)

NASA has demonstrated a resolve to land instruments on the corrosive, high-pressure (~100 bar), high-temperature (470°C) surface of Venus. NASA Glenn Research Center’s JFET-R technology is the only one that has shown 1000’s of hours operation under Venus surface conditions. The limitation of this process is that the current integrated circuit die and feature sizes make it impractical for large complex designs. Ozark IC has developed high-temperature packaging technology capable of integrating several JFET-R die onto a single layer substrate. Complex Venus-surface ICs, such as a microprocessor, can be created by marrying these two technologies.

The objective for this proposal is a multi-chip packaging technology that hosts several JFET-R die to effectively create complex electronic functions for Venus surface conditions.

The project will utilize additive and subtractive manufacturing techniques to create high-temperature single-connector terminals, high temperature/high density multiple conductor connectors, and single or multiple level high-temperature substrates. This, in combination with NASA’s JFET-R technology will create a design technology which will be used to develop a multi-chip high-temperature microprocessor. These advancements in terminal and board manufacturing design should enable denser chip designs. Several prototype connectors will be designed, manufactured, and tested. Once a reliable connector and board system has been identified, an integrated module will be tested at 470°C.

Questions to be answered during the Phase 1 are:

  1. Is it possible to create a high-temperature connector reliable enough for Venus surface conditions?
  2. What package density can be achieved?
  3. What performance can be expected?
Potential NASA Applications (Limit 1500 characters, approximately 150 words)

The proposed packaging technology is the next logical development step for NASA’s JFET-R process towards enabling processing capability on the corrosive, high-pressure (~100 bar), high-temperature (up to 500°C) Venus surface. The system will also be useful for other high temperature environments, such as Mercury, as well as high temperature avionics, re-entry, and propulsion sensing and controls

Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words)

Any application that needs a very high temperature system integration, such as high temperature data processing, measurement or actuation is a potential market. Examples include: geothermal resource exploration to improve drilling efficiency, jet engine sensing and actuation for distributed engine controls, and avionics for high temperature sensing and actuation in hypersonic aircraft.  

Duration: 6
Form Generated on 06/16/2019 23:29:47