NASA SBIR 2017 Solicitation

FORM B - PROPOSAL SUMMARY


PROPOSAL NUMBER: 171 Z6.01-9874
SUBTOPIC TITLE: High Performance Space Computing Technology
PROPOSAL TITLE: Radiation Hardened High Speed Integrated Circuits Double Data Rate I/O for Extreme Operating Environments

SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Microelectronics Research Development Corporation
4775 Centennial Boulevard, Suite 130
Colorado Springs, CO 80919 - 3332
(719) 531-0805

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
Dr. Greg Pauls
greg.pauls@micro-rdc.com
4775 Centennial Boulevard, Suite 130
Colorado Springs, CO 80919 - 3332
(719) 531-0805 Extension :6

CORPORATE/BUSINESS OFFICIAL (Name, E-mail, Mail Address, City/State/Zip, Phone)
Ms. Karen Van Cura
karen.vancura@micro-rdc.com
4775 Centennial Boulevard, Suite 130
Colorado Springs, CO 80919 - 3332
(719) 531-0805 Extension :2

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 1
End: 3

Technology Available (TAV) Subtopics
High Performance Space Computing Technology is a Technology Available (TAV) subtopic that includes NASA Intellectual Property (IP). Do you plan to use the NASA IP under the award?
No

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
Manned and robotic space missions require high-performance electronic control systems capable of operating for extended periods in harsh environments that are subject to radiation, extreme temperatures, vibration and shock. Semiconductor technologies capable of meeting these demanding requirements tend to have limited capabilities, are expensive, and are not easily configured for specific mission requirements. Leading-edge applications will benefit from the ability to implement high speed interconnect protocols between host processors and system slaves, such as sensors, actuators, power managers, imagers and transceivers. The development of a Radiation Hardened Double Data Rate (DDR) embedded macro is proposed for insertion into digital integrated circuits (ICs) suitable for scalable single and multi-core processors, special purpose logic functions and scalable memory blocks on a space-qualified, radiation hardened integrated circuit digital fabric. A NASA-funded Structured ASIC architecture is under development at Micro-RDC, capable of meeting space-grade requirements while creating a cost-effective, quick-turn development environment. The SASIC fabric will implement known Radiation-Hardened-By-Design (RHBD) techniques on an advanced 32nm Silicon on Insulator (SOI) CMOS process, supporting high-density, high-speed low-power implementations. A unique Master Tile architecture with through-seal-ring connections allows the designer to define dedicated logic functions, scalable memory blocks and user-defined I/Os; all on a single, scalable integrated circuit. The 32nm SOI CMOS process technology platform incorporates RHBD building-blocks (e.g. flip-flops, gates, distributed memory, block memory, I/O) required for the systems designer to implement functional blocks for application-specific requirements. During this project, key blocks for a DDR3 macro will be specified and evaluated for optimum inclusion into the Micro-RDC SASIC.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
NASA supports various requirements ranging from science missions, space station, and deep space missions requiring high-performance computing and controls. Interplanetary and long term low Earth orbit systems require radiation tolerances capable of ensuring that the on-board electronics outlast the life expectancy of the systems. These demanding requirements of radiation tolerance and harsh operating environments force satellite systems developers to consider capabilities that are uniquely optimized for their applications. The Structured ASIC solves the dilemma of balancing performance, cost, risk and time to deployment against alternative solutions. Scalable, high performance control systems can support a wide range of applications when integrated circuit flexibility is available. The ability to right-size integrated circuits while adding functional blocks, such as a DDR3 SRAM memory interface, while maintaining performance at low cost, enables NASA to use this technology across a wide range of programs and applications. NASA programs and missions that could benefit include the Thermal Infrared Sensor (TIRS) mission, Climate Absolute Radiance and Refractivity Observatory (CLARREO), BOReal Ecosystem Atmosphere Study (BOREAS) and the Methane Trace Gas Sounder. Longer term missions include lunar landers and orbiters, Mars missions (MAVEN), solar system exploration (e.g. Titan, Juno, Europa, comet nucleus return, New Discovery, and Living with a Star (LWS)).

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Companies that deploy satellites for purposes similar to NASA's Earth-centric applications will greatly benefit by gaining access to the advanced 32nm Silicon on Insulator (SOI) CMOS process technology in a cost efficient manner. There are a number of applications that require this kind of performance within military, intelligence and commercial satellites, which are showing growing demand in units deployed and performance. The 2014 FAA Commercial Space Transportation Forecasts predict that an average of seventy eight commercial payloads will be launched annually over the next decade. A reasonable estimate of the number of classified military and intelligence payloads at least equals the commercial deployments. Micro-RDC currently offers a 90nm CMOS platform, 50MHz Radiation-Hardened-By-Design (RHBD) Structured ASICs capable of handling low to mid-range control and compute requirements in space. The 32nm SOI CMOS platform will increase to 300MHz, and will greatly improve densities and processing speed, including the ability to add DDR3 SRAM memory. This type of memory will enhance functionality for computing applications and peripheral functions such as sensors, actuators, image capture and processing subsystems.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)
Architecture/Framework/Protocols
Autonomous Control (see also Control & Monitoring)
Circuits (including ICs; for specific applications, see e.g., Communications, Networking & Signal Transport; Control & Monitoring, Sensors)
Computer System Architectures
Data Acquisition (see also Sensors)
Image Processing
Models & Simulations (see also Testing & Evaluation)
Network Integration
Quality/Reliability
Robotics (see also Control & Monitoring; Sensors)

Form Generated on 04-19-17 12:59