NASA STTR 2012 Solicitation


PROPOSAL NUMBER: 12-2 T11.01-9699
RESEARCH SUBTOPIC TITLE: Software Framework & Infrastructure Development of Spaceborne Hybrid Multicore/FPGA Architectures
PROPOSAL TITLE: OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs

NAME: RNET Technologies, Inc. NAME: Argonne National Laboratory
STREET: 240 West Elmwood Drive, Suite 2010 STREET: 9700 South Cass Avenue
CITY: Dayton CITY: Lemont
STATE/ZIP: OH  45459 - 4248 STATE/ZIP: IL  60439 - 4803
PHONE: (937) 433-2886 PHONE: (937) 433-2886

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
Chekuri S Choudary
240 W Elmwood Dr., STE 2010
Dayton, OH 45459 - 4248
(937) 433-2886

CORPORATE/BUSINESS OFFICIAL (Name, E-mail, Mail Address, City/State/Zip, Phone)
Vaidyanathan Nagarajan
240 W Elmwood Drive, Suite 2010
Dayton, OH 45459 - 4248
(937) 433-2886

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 3
End: 6

Technology Available (TAV) Subtopics
Software Framework & Infrastructure Development of Spaceborne Hybrid Multicore/FPGA Architectures is a Technology Available (TAV) subtopic that includes NASA Intellectual Property (IP). Do you plan to use the NASA IP under the award?

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently explores the "user tunable" parameter space of an FPGA design and assists in deducing the near optimal design in terms of timing score, device utilization, and power consumption. The tunable parameter space will include IPCore parameters, HDL and HLS code constructs, and parameter settings for the vendor's design tools. Special automation tools will be developed to facilitate annotation of HDL/HLS code and design tool scripts. The computational magnitude of empirical performance tuning of FPGA designs will be addressed by novel machine learning based search algorithms requiring minimal empirical evaluations, computational steering, leveraging intermediate performance analysis results, and parallelization techniques. The tool will support specification of prioritized performance metrics, easy-to-use interfaces for defining the parameter space, and intuitive visualization of performance models. The user will be able to automatically deduce the best environment settings the chip and also accurately identify the optimal power consumption through optional real-time power monitoring. The benefits of the tool to NASA will be demonstrated in terms of performance metrics and cost benefits (user productivity) using real NASA designs that are used in space missions.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
The OrFPGA tool can be used by hardware engineers at NASA and its Prime Contractors to get the incremental performance optimizations required for closing critical FPGA designs in space applications. Potential NASA applications include FPGA implementations on SpaceCube platforms, LCRD algorithms, Pinpoint landing vision components and stereo disparity implementation. The tool will improve both FPGA design performance and developer productivity. The tool will be available as a standalone alone as well as an add-on feature in the existing FPGA design tools.

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Other potential markets could include DoD and its Prime Contractors, DOE, and DHS on the government side as well as medical, communication, and banking industries on the industry side. Example applications include military satellites, portable medical devices, and high frequency trading systems.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)
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Form Generated on 07-29-14 10:30