NASA SBIR 2009 Solicitation

SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone)
Ridgetop Group, Inc.
6595 North Oracle Road
Tucson, AZ 85704 - 5645
(520) 742-3300

PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone)
Justin Judkins
justin.judkins@ridgetopgroup.com
6595 North Oracle Road
Tucson, AZ 85704 - 5645
(520) 742-3300

Estimated Technology Readiness Level (TRL) at beginning and end of contract:
Begin: 4
End: 8

TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words)
In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements.
Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor.
Ridgetop has identified two Phase 2 objectives, which are:
1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits.
2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design.
During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips.
Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.

POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
NASA applications include radar, imaging, detectors, space radio astronomy, and communication circuits. Space radar systems stand to benefit from the combination of high resolution and low power of the proposed ADC. The technology is ideal for NASA Jet Propulsion Laboratory's radar research program, UAVSAR program, and many other critical communication circuits.

POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words)
Non-NASA commercial applications include:
• Phased arrays for ballistic missile defense (BMD) (the DBF technology is commonly cited as a "huge leap" for radar-based missile defense systems)
• Space-based radar for military/intelligence targets or earthquake detection
• Measurement applications, including pin test electronics on ATE systems
• Space navigation systems
• Conformal arrays for UAVs
• Telecommunications applications, such as software-defined radio
• Medical imaging device manufacturers
• Computer networks, hard disk readout circuits, digital oscilloscopes, etc. ; these applications require 500 MSPS sampling speeds, and the "effective number of bits" (ENOB) used in contemporary converters is <10 bits, and the power dissipation is >2 W
• Power-limited applications, such as laptops, wireless devices and PDAs.

TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.)

Guidance, Navigation, and Control Microwave/Submillimeter Radiation-Hard/Resistant Electronics Telemetry, Tracking and Control